1. Field of the Invention
The invention relates to semiconductor technology and in particular to a semiconductor device with local interconnects having low contact resistance.
2. Description of the Related Art
For the fabrication of semiconductor integrated circuits, the size of semiconductor devices in the integrated circuits, such as transistors, resistors, capacitors or other semiconductor elements well known in the art, has been continuously reduced in order to increase device density. Accordingly, a multi-layered interconnect structure is typically required for electrical connection of the individual semiconductor devices. Along with reduction in the size and dimension of semiconductor devices, more components are being placed on an integrated circuit or die, which increases design complexity of the multi-layered interconnect structure.
Typically, the multi-layered interconnect structure comprises plugs and metal layers, which are provided by a conventional dual damascene process. In the dual damascene process, via openings are first anisotropically etched through an inter-metal dielectric (IMD)/interlayer dielectric (ILD) layer by a conventional photolithography and etching process. A second anisotropically etched opening referred to as a trench opening is then formed overlying one or more of the via openings by a second photolithography and etching process. The via openings and the trench opening together makeup the dual damascene structure which is subsequently filled with metal to form plugs and metal layers. As the size and dimension of semiconductor devices are reduced, the size of plugs is also reduced, thus increasing the aspect ratio of the via openings, which decreases fabrication yields. Aspect ratio is defined herein as the height/width ratio of the via opening. As the aspect ratio increases, the contact resistance of the plugs increases. Accordingly, as device density increases, it becomes more difficult to maintain or increase the electrical properties and the reliability of the devices.
Therefore, there exists a need for an improved interconnect structure, which is capable of reducing contact resistance as the size of a device is reduced to increase device density.